RISC-V Server Platform Specification Ratified
https://github.com/riscv-non-isa/riscv-server-platform/releases/tag/v1.0

https://redd.it/1t72lw6
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Sipeed says K3 boards are in their online store this weekend
https://x.com/SipeedIO/status/2052596802592067872

https://redd.it/1t72bts
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Ziccid Extension for Instruction and Data Coherence and Consistency To Be Ratified in June
https://riscv.atlassian.net/browse/RVS-3933

https://redd.it/1t72o7u
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Skopx — AI analytics platform with 50+ data connectors
https://skopx.com

https://redd.it/1t7fzb5
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011111 rule for 48-bit instructions

If the encoding space for 32-bit instructions is getting tight (which is apparently a concern?), why would it not make sense for the encoding of 48-bit instructions to be slanted one further bit to the left by using 0111111 to mark the beginning instead of 011111? From what I can tell this should double the number of available major opcodes for 32-bit instructions (the most common case), fits neatly in the 7-bit opcode segment and is barely any extra decode complexity. Is it because the current arrangement leaves the most room for the largest instructions? Is the encoding space not as problematic?

https://redd.it/1t736p2
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BL616 Web Flasher!
https://philmillman.github.io/M0SSFlash/

https://redd.it/1t7pusr
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Dabao SDK Bare Metal C SDK for the Baochip-1x RISC-V SoC

The Dabao board featuring the Baochip-1x designed by legendary hardware hacker bunnie Huang had its crowd supply run and boards are due to ship later this year..I had the pleasure over the past month or so of writing a bare metal C SDK for the board before it ships put and production ramps up later this year...

The SDK is similar to how the PICO does stuff and there is no FFI layer or dependencies beyond a standard RISC-V GCC cross compiler....

It's Apache 2.0 and has peripheral drivers and examples that cover almost eveeything you can use on the Dabao board...ofc the UDMA architecture means all peripherlas use the UDMA DMA engine for data transfers and I have borh blocking and non-blocking APIs for comms though it wont be needed as this thing has a 700 MHz BIO coprocessor that can blaze any protocol fro high speed independent bit-banging...

I tried to make the API intebtionally PICO style, so that anyone who's written C for the PICO will feel at home....

Register defintion headers are included so you can drop down to raw hardware access when you need too, my aim was to have a simple but powerful SDK, high level enough for rapid development but low level enough that hardware is never hidden from you...

Developing while being able to look at the RTL was surreal!! It made me move way faster than I would have otherwise and the unique architecture of the chip would have made it different otherwise!!

In case anyone is curious about how you program this chip, I hope this SDK will help you out until you get your boards...trust me when you can grab ome of these things I can't put them down, SoC in MCU form factor its very very fun to work with...

You can look at the SDK on Github here, its Apache 2.0 license so knock yourselfs out, I'll be updating and ironing out any bugs as the weeks go by!

https://github.com/ArmstrongSubero/dabao-sdk

https://redd.it/1t7rk48
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openRuyi 2026.04 Released

openRuyi is an open source, rolling-release Linux distribution for RISC-V.


`openruyi.cn/news/releases/2026-04`

https://redd.it/1t7sgzq
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Now at https://sipeed.com/k3 ...
https://redd.it/1t8svg5
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RISC-V Serial Debug Protocol (draft)
https://gitlab.com/lauterbach/riscv-rsdp-spec

https://redd.it/1t95t4k
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SpacemiT X100 clang benchmark with and without RVC
https://redd.it/1t9bzku
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libsbicall - a C wrapper library for SBI calls

I translated the current SBI spec into a small library that provides C functions for interfacing with SBI:

https://github.com/krakenlake/libsbicall

Any feedback welcome!

https://redd.it/1t9ibud
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Thoughts on using the K3

So the varying VLEN across the x100 and a100 core cluster is going to make the a100 cluster harder to use -- we can't just present it as a 16c system where processes run wherever they want and migrate freely.


I'm not likely ever going to bother trying to explicitly launch things on the a100 cluster or setting up distcc to use that cluster (distcc would only help marginally for cases I care about). *But* I could easily see standing up a docker container on the a100 cluster and opening ports to make it appear as-if the a100 cluster is a distinct system. I can also limit the docker containe for the a100 to 16G of memory, which I already know is sufficient for my needs.

The net is I think I can utilize both cpu clusters meaningfully. A single unified 16c system would be best, but this is a viable second-best option AFAICT.

https://redd.it/1t9no7a
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[somewhat off-topic] The SPEC CPU 2026 Benchmark Released
https://www.spec.org/cpu2026/

https://redd.it/1t9xbn5
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Milk-V Jupiter 2 is now available

I got finally an email from https://arace.tech that the Milk-V Jupiter 2 is now available.

Seems it is only the base version and not the dev kit that are available.

I ordered the 16GB version, for a board that I probably do not need ;-)

https://redd.it/1ta1pe5
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Firefly launches mini PC powered by SpacemiT K3 RISC-V SoC
https://www.cnx-software.com/2026/05/12/firefly-aibox-k3-an-edge-ai-mini-pc-powered-by-spacemit-k3-risc-v-soc/

https://redd.it/1tavgde
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The Development of SpacemiT X200 Based on XiangShan Kunminghu V2 Completed
https://github.com/OpenXiangShan/XiangShan-doc/pull/246

https://redd.it/1tayb6c
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SiFive introduces RVA23-compliant Performance P570 Gen3 RISC-V core for consumer and AIoT applications
https://www.cnx-software.com/2026/05/12/sifive-performance-p570-gen3-rva23-compliant-risc-v-core-consumer-aiot-applications/

https://redd.it/1tb1dem
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