lt
1 1 1.00 U ret

​

**comapre 2 - clang 8 -O3 -DNDEBUG -mcpu=cortex-a73 (gcc stl)**

Instructions: 25
Total Cycles: 22
Total uOps: 25
Dispatch Width: 3
uOps Per Cycle: 1.14
IPC: 1.14
Block RThroughput: 9.0

Instruction Info:
[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)

[1] [2] [3] [4] [5] [6] Instructions:
1 4 1.00 * ldr x8, [x0, #8]
1 4 1.00 * ldr x9, [x1, #8]
1 1 0.50 cmp x8, x9
1 1 1.00 b.ge .LBB0_2
1 1 0.50 orr w0, wzr, #0x1
1 1 1.00 U ret
1 1 0.50 cmp x9, x8
1 1 1.00 b.ge .LBB0_4
1 1 0.50 mov w0, wzr
1 1 1.00 U ret
1 4 1.00 * ldr w8, [x0, #4]
1 4 1.00 * ldr w9, [x1, #4]
1 1 0.50 cmp w8, w9
1 1 1.00 b.ge .LBB0_6
1 1 0.50 orr w0, wzr, #0x1
1 1 1.00 U ret
1 1 0.50 cmp w9, w8
1 1 1.00 b.ge .LBB0_8
1 1 0.50 mov w0, wzr
1 1 1.00 U ret
1 4 1.00 * ldr w8, [x0]
1 4 1.00 * ldr w9, [x1]
1 1 0.50 cmp w8, w9
1 1 0.50 cset w0, lt
1 1 1.00 U ret

**comapre 2 - gcc 8.3 -O3 -DNDEBUG -mcpu=cortex-a73 (gcc stl)**

Instructions: 22
Total Cycles: 15
Total uOps: 22
Dispatch Width: 3
uOps Per Cycle: 1.47
IPC: 1.47
Block RThroughput: 7.3
Instruction Info:

[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)

[1] [2] [3] [4] [5] [6] Instructions:
1 4 1.00 * ldr x3, [x0, #8]
1 4 1.00 * ldr x2, [x1, #8]
1 1 0.50 cmp x3, x2
1 1 1.00 b.lt .L3
1 1 0.50 mov w2, #0
1 1 1.00 b.ne .L2
1 4 1.00 * ldr w4, [x0, #4]
1 1 0.50 mov w2, #1
1 4 1.00 * ldr w3, [x1, #4]
1 1 0.50 cmp w4, w3
1 1 1.00 b.lt .L2
1 1 0.50 mov w2, #0
1 1 1.00 b.ne .L2
1 4 1.00 * ldr w2, [x0]
1 4 1.00 * ldr w0, [x1]
1 1 0.50 cmp w2, w0
1 1 0.50 cset w2, lt
1 1 0.50 mov w0, w2
1 1 1.00 U ret
1 1 0.50 mov w2, #1
1 1 0.50 mov w0, w2
1 1 1.00 U ret

https://redd.it/bejzq5
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