https://github.com/xoreaxeaxeax/asm-hall-of-shame
Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
🏆 Current Champions 🏆
x86: fxrstor64
Strategy: Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions, so CPU 0's 512-byte fxrstor64 must queue behind all that contending traffic.
🏆 Score: 198,002,498,236 cycles
🏆 Time: 62 seconds
GitHub
GitHub - xoreaxeaxeax/asm-hall-of-shame: Racing to the bottom of CPU performance
Racing to the bottom of CPU performance. Contribute to xoreaxeaxeax/asm-hall-of-shame development by creating an account on GitHub.
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给 scribble.meow.plus 加了个目录
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Forwarded from 猫咪阅读频道
Steve Awodey
Lecture notes for Categorical Logic
Steve Awodey's GitHub pages
Forwarded from slanterns w/ 🦀
GitHub
make closures act like MaybeDangling by RalfJung · Pull Request #160745 · rust-lang/rust
This makes closures (and types like them: coroutines and coroutine closures) act like MaybeDangling. This means that the aliasing model will entirely ignore references and Boxes passed around as cl...