Forwarded from Hacker News (yahnc_bot)
We finally learned to center a div, then browsers added sidebars https://seg6.space/posts/center-div/
seg6
we finally learned to center a div, then browsers added sidebars
an extension for centering a page in the browser window instead of the webview.
Forwarded from Hacker News (yahnc_bot)
Bubble Memory https://en.wikipedia.org/wiki/Bubble_memory
Wikipedia
Bubble memory
type of non-volatile computer memory
Forwarded from 一个存在的世界 (Miao Wu)
Chipsandcheese
NVIDIA’s Vera Whitepaper Has a Thread Loose
Hello you fine Internet folks,
Forwarded from 木ノ幡みら🍭🌻
X (formerly Twitter)
武者ねこ (@musyanekoo) on X
ご依頼ありがとうございました！
さくら、もゆのクロです。
ちからつきた
さくら、もゆのクロです。
ちからつきた
🥰2
Forwarded from Hacker News (yahnc_bot)
NIST
How Do Atomic Clocks Work?
Credit: N. Hanacek/NIST
https://github.com/xoreaxeaxeax/asm-hall-of-shame
Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
🏆 Current Champions 🏆
x86: fxrstor64
Strategy: Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions, so CPU 0's 512-byte fxrstor64 must queue behind all that contending traffic.
🏆 Score: 198,002,498,236 cycles
🏆 Time: 62 seconds
GitHub
GitHub - xoreaxeaxeax/asm-hall-of-shame: Racing to the bottom of CPU performance
Racing to the bottom of CPU performance. Contribute to xoreaxeaxeax/asm-hall-of-shame development by creating an account on GitHub.
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