#comp_arch

When dealing with control hazards, we need to predict the next instructions and flush the pipeline registers if the branch is taken. Since the branch checks whether rs = rt, we can put an equality comparator in the Decode stage, thus reducing the penalty of a misprediction. The interesting thing is that by doing that, we need to deal with RAW (read after write) hazards, because of the equality comparator sources, the process is similar to the post above. If the sources are in the Writeback stage, there is no hazard (the write step is made at low clock, and the read step is made at high clock). If the sources are in the Memory stage, we use a simple logic as the picture shows (ForwardAD and ForwardBD), take a look at the combinatory logic, i will not explain. Now, if the sources are in the Execute stage or in the Memory stage of a lw instruction, the Decode stage will be stalled and the Execute stage will be flushed.