[WiP] PCI2Nano - An open source FPGA PCI (not PCI-E) core, a 8250-Compatible PCI-based UART core and Nios II example design driving the UART.
Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!
Links:
β«οΈ gateware
β«οΈ hardware
#PCI #verilog #UART #8250 #NIOS
Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!
Links:
β«οΈ gateware
β«οΈ hardware
#PCI #verilog #UART #8250 #NIOS
π1
parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.
It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.
Links:
β«οΈ Documentation
β«οΈ Sources
#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores
It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.
Links:
β«οΈ Documentation
β«οΈ Sources
#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores
GitHub
parser-gen/README.parse-graphs.md at master Β· grg/parser-gen
Network packet parser generator. Contribute to grg/parser-gen development by creating an account on GitHub.
GLIP - The Generic Logic Interfacing Project.
GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.
Features
β«οΈEasy FIFO-based communication, abstracting away all low-level details
β«οΈSupport for different communication channels through backends
β«οΈSide-channel communication (e.g. reset signals)
β«οΈDeveloped on and for Linux
Links:
β«οΈ Documentation
β«οΈ Sources
#verilog #SV #JTAG #FIFO #USB
@ipcores
GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.
Features
β«οΈEasy FIFO-based communication, abstracting away all low-level details
β«οΈSupport for different communication channels through backends
β«οΈSide-channel communication (e.g. reset signals)
β«οΈDeveloped on and for Linux
Links:
β«οΈ Documentation
β«οΈ Sources
#verilog #SV #JTAG #FIFO #USB
@ipcores
Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
Links:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
@ipcores
β«οΈ
lfsr.v - Parametrizable combinatorial LFSR/CRC moduleβ«οΈ
lfsr_crc.v - Parametrizable CRC computation wrapperβ«οΈ
lfsr_descramble.v - Parametrizable LFSR self-synchronizing descramblerβ«οΈ
lfsr_prbs_check.v - Parametrizable PRBS checker wrapperβ«οΈ
lfsr_prbs_gen.v - Parametrizable PRBS generator wrapperβ«οΈ
lfsr_scramble.v - Parametrizable LFSR self-synchronizing scramblerLinks:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
@ipcores
π1
SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
svo_defines.vh for details on those parameters.Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
π1π1
Vortex - a full-system RISCV-based GPGPU processor.
Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
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Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π1
LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio.
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
π5
700 followers π±
Thank you to everyone of you! ππ»
Thank you to everyone of you! ππ»
Vortex - a full-system RISCV-based GPGPU processor
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π2β€1
Cryptography IP-cores lib
Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
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Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
@ipcores
π3π₯1
SVLogger - A SystemVerilog logger to help designers to log events in a circuit during a simulation in a consistent way. SVLogger is a simple class, easy to instantiate and use, with no dependencies.
πΎ https://github.com/dpretet/svlogger
π https://github.com/dpretet/svlogger/tree/main/example
#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
@ipcores
πΎ https://github.com/dpretet/svlogger
π https://github.com/dpretet/svlogger/tree/main/example
#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
@ipcores
SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
π₯11π8π€1π1
open5G_rx - a synthesizable verilog HDL core for a 5G NR lower phy receiver.
Implemented:
β«οΈ Decimator
β«οΈ PSS correlator
β«οΈ Peak detector
β«οΈ PSS detector
β«οΈ FFT demodulator
β«οΈ SSS detector
β«οΈ Frame sync
β«οΈ Channel estimator
β«οΈ Ressource grid subscriber
β«οΈ AXI-DMAC
πΎ https://github.com/catkira/open5G_rx
#SV #5G #DSP #FFT #ORAN
@ipcores
Implemented:
β«οΈ Decimator
β«οΈ PSS correlator
β«οΈ Peak detector
β«οΈ PSS detector
β«οΈ FFT demodulator
β«οΈ SSS detector
β«οΈ Frame sync
β«οΈ Channel estimator
β«οΈ Ressource grid subscriber
β«οΈ AXI-DMAC
πΎ https://github.com/catkira/open5G_rx
#SV #5G #DSP #FFT #ORAN
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π11β€4π₯4π±4β‘1
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design.
Features:
β«οΈ802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
β«οΈ20MHz bandwidth; 70 MHz to 6 GHz frequency range
β«οΈMode tested: Ad-hoc; Station; AP, Monitor
β«οΈDCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
β«οΈ802.11 packet injection and fuzzing
β«οΈCSI: Channel State Information, freq offset, equalizer to computer
β«οΈCSI fuzzer: Create artificial channel response in WiFi transmitter
β«οΈCSI radar: Moving detection. Joint radar and communication
β«οΈIQ capture: real-time AGC, RSSI, IQ sample to computer
β«οΈConfigurable channel access priority parameters
β«οΈTime slicing based on MAC address (time gated/scheduled FPGA queues)
β«οΈEasy to change bandwidth and frequency:
β«οΈ2MHz for 802.11ah
β«οΈ10MHz for 802.11p
Links:
π https://github.com/open-sdr/openwifi
πΎ https://github.com/open-sdr/openwifi-hw
#SV #80211 #SDR #DSP #wifi
@ipcores
Features:
β«οΈ802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
β«οΈ20MHz bandwidth; 70 MHz to 6 GHz frequency range
β«οΈMode tested: Ad-hoc; Station; AP, Monitor
β«οΈDCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
β«οΈ802.11 packet injection and fuzzing
β«οΈCSI: Channel State Information, freq offset, equalizer to computer
β«οΈCSI fuzzer: Create artificial channel response in WiFi transmitter
β«οΈCSI radar: Moving detection. Joint radar and communication
β«οΈIQ capture: real-time AGC, RSSI, IQ sample to computer
β«οΈConfigurable channel access priority parameters
β«οΈTime slicing based on MAC address (time gated/scheduled FPGA queues)
β«οΈEasy to change bandwidth and frequency:
β«οΈ2MHz for 802.11ah
β«οΈ10MHz for 802.11p
Links:
π https://github.com/open-sdr/openwifi
πΎ https://github.com/open-sdr/openwifi-hw
#SV #80211 #SDR #DSP #wifi
@ipcores
β€9π5β‘4π₯2β€βπ₯1
SlowDDR3 - A general slow DDR3 interface.
Features:
β«οΈVery little resource consumption*
β«οΈSuits for all FPGAs with 1.5V IO voltage
β«οΈDesigned to run at DDR-100
β«οΈDesigned to work with LVCMOS IO PADs
β«οΈWrite in SpinalHDL (Future is coming π )
*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.
Links:
πΎ src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
π example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test
#DDR3 #SDRAM #SpinalHDL
@ipcores
Features:
β«οΈVery little resource consumption*
β«οΈSuits for all FPGAs with 1.5V IO voltage
β«οΈDesigned to run at DDR-100
β«οΈDesigned to work with LVCMOS IO PADs
β«οΈWrite in SpinalHDL (Future is coming π )
*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.
Links:
πΎ src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
π example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test
#DDR3 #SDRAM #SpinalHDL
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π₯5π3β€1β€βπ₯1π1
USB_CDC - Full Speed (12Mbit/s) USB communications device class (or USB CDC class) for FPGA and ASIC designs.
USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (
macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like
πΎ https://github.com/ulixxe/usb_cdc
#USB #CDC #UART #verilog
@ipcores
USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (
Usbser.sys) for USB CDC devices. A USB_CDC device is automatically recognized by Windows 10 as a virtual COM port, and a serial port terminal application such as CoolTerm can be used to communicate with it.macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like
/dev/cu.usbmodem14601, whereas, on Linux, it gets a name like /dev/ttyACM0.πΎ https://github.com/ulixxe/usb_cdc
#USB #CDC #UART #verilog
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π19π₯8π1
USB_HID_host - a compact USB HID host FPGA core supporting keyboards, mice and gamepads.
It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).
Features:
β«οΈNo CPU is required. The core handles all layers of the USB protocol related to HID devices
β«οΈNo USB interface IC (PHY) needed
β«οΈUSB low-speed (1.5Mbps). Uses a single 12Mhz clock
πΎ https://github.com/nand2mario/usb_hid_host
#USB #HID #host #verilog
@ipcores
It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).
Features:
β«οΈNo CPU is required. The core handles all layers of the USB protocol related to HID devices
β«οΈNo USB interface IC (PHY) needed
β«οΈUSB low-speed (1.5Mbps). Uses a single 12Mhz clock
πΎ https://github.com/nand2mario/usb_hid_host
#USB #HID #host #verilog
@ipcores
π17β€2