GRVI is an FPGA-efficient RISC-V RV32I soft processor core, hand technology mapped and floorplanned for best performance/area as a processing element (PE) in a parallel processor. GRVI implements a 2 or 3 stage single issue pipeline, typically consumes 320 6-LUTS in a Xilinx UltraScale FPGA, and currently runs at 300-375 MHz in a Kintex UltraScale (-2) in a standalone configuration with most favorable placement of local BRAMs.
https://fpga.org/grvi-phalanx/
#RISC-V #ParallelProcessing #NOC #ParallelComputing #Phalanx #Hoplite

USB 2.0 FS Device controller IP core

https://github.com/esynr3z/usb20dev
#USB #UNDERDEVELOPMENT #FullSpeed #SV

Verilog RTL for S27KL0641DABHI020 64Mbit HyperRAM

https://github.com/blackmesalabs/hyperram
#HyperRAM #verilog #Cypress

HyperRAM controller for Lattice iCE40 UltraPlus FPGA
https://github.com/gtjennings1/HyperBUS

Cypress HyperRAM Verilog model (S27KL0641)
https://www.cypress.com/verilog/s27kl0641-verilog

#HyperRAM #verilog #Cypress #ISSI #LatticeSemi #S27KL0641

HyperRAM Controller from Intel
Cyclone® 10LP: around 300 LEs, 2 M9Ks, up to 166MHz
https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/a-l-s-e/ip/hyperram-controller.html

#HyperRAM #verilog #Cypress #ISSI

Collections of #MIPI related IP-cores on #Verilog:

#CSI
CSI-2 receiver for Xilinx UltraScale [https://github.com/stevenbell/csirx]
4k CSI-2 Rx core for Xilinx FPGA [https://github.com/daveshah1/CSI2Rx]

#DSI
Lattice iCE40UP FPGA to LH154Q01 Display [https://github.com/gtjennings1/UPDuino-LH154Q01-Display]
Arduino MIPI DSI Shield [https://github.com/twlostow/dsi-shield]

SystemVerilog FIFO and CDC-components

https://github.com/runsler/library
#SV #FIFO #resynchronization #CDC

FPGA implementation of true random generator on Self-timed Rings.
Maximum speed for best random quality is 0.5 Mbit/s.

https://github.com/esynr3z/strng
https://ieeexplore.ieee.org/document/7332773
#RNG #TRNG #random #verilog

DDR3 memory controller that does not depend on any non-documented features of Xilinx FPGA and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.

https://github.com/Elphel/eddr3
https://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/
#DDR3 #Xilinx #AXI

USB3 core:
USB2/ULPI & USB3/PIPE are working.

The design currently uses a TUSB1310A for interfacing with the USB3.0 connector. Future plans include replacing this part using the high speed transceivers (GTPs/GTXs) found in Artix-7/Kintex-7 FPGAs.

https://github.com/enjoy-digital/daisho

#USB2 #USB3 #verilog #TUSB1310A #Xilinx

PCIe DMA Engine for Xilinx FPGA

Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block. Core is specifically designed for the 256 bit wide AXI4-Stream interface of the Xilinx FPGA HardBlock PCIe Gen3. Core has been also successfully ported to Xilinx Kintex UltraScale FPGA.

https://opencores.org/projects/virtex7_pcie_dma

#PCIe #DMA #Xilinx #VHDL #AXIS
@ipcores

FlexPRET is a 5-stage, fine-grained multithreaded #RISCV processor designed specifically for mixed-criticality (real-time embedded) systems and written in #Chisel

https://github.com/pretis/flexpret
@ipcores