جلسه یازدهم - 4variable maps - All NOR - Product of Sums - POS - Maxterms - Breaking NANDS,NOR - 2input gates - longest path

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جلسه دوازدهم - Timing - Hazards - Potential Hazards - Logical Hazards - Electrical Hazarads

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جلسه سیزدهم - Tabular minimization - Cubical representation - PI , EPI using tabular method

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جلسه چهاردهم - RTL components - Flow from transistors , gate , RTL - Elements of RT level design - Activity levels - 2-4 Decoder - Cascading decoders - 4- to -16 decoders - 2-to-1

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جلسه پانزدهم - Decoder verilog - Multiplexer - Tri -State - Cascading MUX

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جلسه شانزدهم - Multiplexer Tri-state - Using MUX for random logic - Full & half adder - 4bit adder - Subtrator - adder Subtractor - Adder verilog

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جلسه هفدهم - Parity circuit - Verilog for parity - Generate stataement coparator - iterative 1bit comparator - Magnitude comparator

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جلسه هجدهم - Fast adders - bit level - block level - Group propogate & generate - 2bit adder -

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جلسه نوزدهم - Adders - Carry skip adder - Priority encoders - Cascadable priority encoder - ALU - 8function ALU - input sensitivity - output in always statement - complete verilo
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جلسه بیستم - PLD:programmable - Logic devices - ROM -ROM evolotion - PROM - EPROM - EEPROM

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جلسه بیست و یکم - ROM - PLA folding - Programmable array - Logic , product term expansion - CPLD - Multiple PALs - FPGA structure - Evalution of FPGAs

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جلسه بیست و دوم - D-latch - Resolving the transparancies - JK Flip-Flop - Toggol Filp-Flop - Binary counter with TFF - Synchronous counter

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جلسه بیست و سوم - آشنایی با نرم افزار

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جلسه بیست و چهارم - Flip -Flop - D-type Flip Flop - Transition - edge Trigger - Rising & Falling edge

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جلسه بیست و پنجم - Cross -coupled Latch - Serial input right shfter - Verilog description - Parallel load - Ring counters twisted

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جلسه بیست و ششم - Counters - Hoffman model - Carry in & out and load input - Divider

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جلسه بیست و هفتم - Random counter - State diagram for controller - Datapath componenets - Controller state diagram

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جلسه بیست و هشتم- State machines - Present state - Next state - Hoffman model - Moone machine timing - Mealy machine timing - Sequence detected

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جلسه بیست و نهم - RT level design flow - Datapath - Controller - Intra-RTL communication - Worst case analysis - Clock duration - First RT level design - Serial adder

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جلسه سی ام - Multiplator datapath - Multiliplior controller - Start- ready handshaking - Controller state diagram - Datapath verilog description

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