hq-logic-fa-9.mp4
151.6 MB
جلسه نهم - Boolean Algebra examples - Truth table karnaugh map - Produnt term - Sum of products - Standard SOP - combining of minterms
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-10.mp4
223.8 MB
جلسه دهم - Implicant - PI -EPI - Unique functions - Using EPI analysis -3&4 variable maps
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🆑 @Engineer_Computer
hq-logic-fa-11.mp4
229.2 MB
جلسه یازدهم - 4variable maps - All NOR - Product of Sums - POS - Maxterms - Breaking NANDS,NOR - 2input gates - longest path
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-12.mp4
208.6 MB
جلسه دوازدهم - Timing - Hazards - Potential Hazards - Logical Hazards - Electrical Hazarads
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-13.mp4
170.5 MB
جلسه سیزدهم - Tabular minimization - Cubical representation - PI , EPI using tabular method
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-14.mp4
231.4 MB
جلسه چهاردهم - RTL components - Flow from transistors , gate , RTL - Elements of RT level design - Activity levels - 2-4 Decoder - Cascading decoders - 4- to -16 decoders - 2-to-1
🆑 @Engineer_Comput
🆑 @Engineer_Comput
hq-logic-fa-16.mp4
227.2 MB
جلسه شانزدهم - Multiplexer Tri-state - Using MUX for random logic - Full & half adder - 4bit adder - Subtrator - adder Subtractor - Adder verilog
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-17.mp4
252.9 MB
جلسه هفدهم - Parity circuit - Verilog for parity - Generate stataement coparator - iterative 1bit comparator - Magnitude comparator
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-18.mp4
177.1 MB
جلسه هجدهم - Fast adders - bit level - block level - Group propogate & generate - 2bit adder -
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-19.mp4
373.7 MB
جلسه نوزدهم - Adders - Carry skip adder - Priority encoders - Cascadable priority encoder - ALU - 8function ALU - input sensitivity - output in always statement - complete verilo
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-20.mp4
236.9 MB
جلسه بیستم - PLD:programmable - Logic devices - ROM -ROM evolotion - PROM - EPROM - EEPROM
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-21.mp4
243.6 MB
جلسه بیست و یکم - ROM - PLA folding - Programmable array - Logic , product term expansion - CPLD - Multiple PALs - FPGA structure - Evalution of FPGAs
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-22.mp4
235.4 MB
جلسه بیست و دوم - D-latch - Resolving the transparancies - JK Flip-Flop - Toggol Filp-Flop - Binary counter with TFF - Synchronous counter
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-24.mp4
262.2 MB
جلسه بیست و چهارم - Flip -Flop - D-type Flip Flop - Transition - edge Trigger - Rising & Falling edge
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-25.mp4
264.5 MB
جلسه بیست و پنجم - Cross -coupled Latch - Serial input right shfter - Verilog description - Parallel load - Ring counters twisted
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-26.mp4
175.1 MB
جلسه بیست و ششم - Counters - Hoffman model - Carry in & out and load input - Divider
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-27.mp4
205.6 MB
جلسه بیست و هفتم - Random counter - State diagram for controller - Datapath componenets - Controller state diagram
🆑 @Engineer_Computer
🆑 @Engineer_Computer
hq-logic-fa-28.mp4
240.1 MB
جلسه بیست و هشتم- State machines - Present state - Next state - Hoffman model - Moone machine timing - Mealy machine timing - Sequence detected
🆑 @Engineer_Computer
🆑 @Engineer_Computer