جلسه هفتم - Transistor logic - Pass transistors & threshold drop - Week 1 & weak 0 - Transmission gate - MUX using pass transistors - Ratioed logic - AOI verilog

🆑 @Engineer_Computer

جلسه هشتم - Overflow circuit implementation - Gate level implementation - Verilog gate level - Verilog using assign statement - Transistor count and delay

🆑 @Engineer_Computer

جلسه نهم - Boolean Algebra examples - Truth table karnaugh map - Produnt term - Sum of products - Standard SOP - combining of minterms

🆑 @Engineer_Computer

جلسه دهم - Implicant - PI -EPI - Unique functions - Using EPI analysis -3&4 variable maps

🆑 @Engineer_Computer

جلسه یازدهم - 4variable maps - All NOR - Product of Sums - POS - Maxterms - Breaking NANDS,NOR - 2input gates - longest path

🆑 @Engineer_Computer

جلسه دوازدهم - Timing - Hazards - Potential Hazards - Logical Hazards - Electrical Hazarads

🆑 @Engineer_Computer

جلسه سیزدهم - Tabular minimization - Cubical representation - PI , EPI using tabular method

🆑 @Engineer_Computer

جلسه چهاردهم - RTL components - Flow from transistors , gate , RTL - Elements of RT level design - Activity levels - 2-4 Decoder - Cascading decoders - 4- to -16 decoders - 2-to-1

🆑 @Engineer_Comput

جلسه پانزدهم - Decoder verilog - Multiplexer - Tri -State - Cascading MUX

🆑 @Engineer_Computer

جلسه شانزدهم - Multiplexer Tri-state - Using MUX for random logic - Full & half adder - 4bit adder - Subtrator - adder Subtractor - Adder verilog

🆑 @Engineer_Computer

جلسه هفدهم - Parity circuit - Verilog for parity - Generate stataement coparator - iterative 1bit comparator - Magnitude comparator

🆑 @Engineer_Computer

جلسه هجدهم - Fast adders - bit level - block level - Group propogate & generate - 2bit adder -

🆑 @Engineer_Computer

جلسه نوزدهم - Adders - Carry skip adder - Priority encoders - Cascadable priority encoder - ALU - 8function ALU - input sensitivity - output in always statement - complete verilo
🆑 @Engineer_Computer

جلسه بیستم - PLD:programmable - Logic devices - ROM -ROM evolotion - PROM - EPROM - EEPROM

🆑 @Engineer_Computer

جلسه بیست و یکم - ROM - PLA folding - Programmable array - Logic , product term expansion - CPLD - Multiple PALs - FPGA structure - Evalution of FPGAs

🆑 @Engineer_Computer

جلسه بیست و دوم - D-latch - Resolving the transparancies - JK Flip-Flop - Toggol Filp-Flop - Binary counter with TFF - Synchronous counter

🆑 @Engineer_Computer

جلسه بیست و سوم - آشنایی با نرم افزار

🆑 @Engineer_Computer

جلسه بیست و چهارم - Flip -Flop - D-type Flip Flop - Transition - edge Trigger - Rising & Falling edge

🆑 @Engineer_Computer

جلسه بیست و پنجم - Cross -coupled Latch - Serial input right shfter - Verilog description - Parallel load - Ring counters twisted

🆑 @Engineer_Computer

جلسه بیست و ششم - Counters - Hoffman model - Carry in & out and load input - Divider

🆑 @Engineer_Computer