#اینفوگرافیک : راهنمای مفاهیم پایه #بیت‌کوین بخش اول
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📌 @Engineer_Computer

🌀 آموزش مدارهای منطقی
▫️زبان فارسی
▫️استاد : دکتر زین العابدین نوابی
▫️34 ویدئوی آموزشی
▫️حجم 7.2GB
▫️منبع : مکتب خونه (دانشگاه تهران)

🔰 دانلود از کانال آموزش کامپیوتر 👇

🆑 @Engineer_Computer

معرفی درس و استاد زین العابدین نوابی

🆑 @Engineer_Computer

جلسه اول - introduction،Digital Design،From switches to complete systems،Design methods

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جلسه دوم - Numbers،Integers،Fractional،Hex& Octal،BCD،Gray code،Excess-3

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جلسه سوم -Coding systems،Acii،Arithmetic،Signed & unsigned،2's complement and examples،Overflow ،Sign extension

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جلسه چهارم - Transistor structure - Transistor Model - Logic value system - Verilog transistor model - Transistor delay parameteres - Building an inverter - Inverter timing
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جلسه پنجم - Inverter transistorlevel - Inverter verliog description

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جلسه ششم - Gate structires - NAND gate cmos - NOR gate cmos - MUX gate structure - XOR gate structures

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جلسه هفتم - Transistor logic - Pass transistors & threshold drop - Week 1 & weak 0 - Transmission gate - MUX using pass transistors - Ratioed logic - AOI verilog

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جلسه هشتم - Overflow circuit implementation - Gate level implementation - Verilog gate level - Verilog using assign statement - Transistor count and delay

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جلسه نهم - Boolean Algebra examples - Truth table karnaugh map - Produnt term - Sum of products - Standard SOP - combining of minterms

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جلسه دهم - Implicant - PI -EPI - Unique functions - Using EPI analysis -3&4 variable maps

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جلسه یازدهم - 4variable maps - All NOR - Product of Sums - POS - Maxterms - Breaking NANDS,NOR - 2input gates - longest path

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جلسه دوازدهم - Timing - Hazards - Potential Hazards - Logical Hazards - Electrical Hazarads

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جلسه سیزدهم - Tabular minimization - Cubical representation - PI , EPI using tabular method

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جلسه چهاردهم - RTL components - Flow from transistors , gate , RTL - Elements of RT level design - Activity levels - 2-4 Decoder - Cascading decoders - 4- to -16 decoders - 2-to-1

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جلسه پانزدهم - Decoder verilog - Multiplexer - Tri -State - Cascading MUX

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جلسه شانزدهم - Multiplexer Tri-state - Using MUX for random logic - Full & half adder - 4bit adder - Subtrator - adder Subtractor - Adder verilog

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جلسه هفدهم - Parity circuit - Verilog for parity - Generate stataement coparator - iterative 1bit comparator - Magnitude comparator

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جلسه هجدهم - Fast adders - bit level - block level - Group propogate & generate - 2bit adder -

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